1. Field of the Invention
This invention relates to a word line clamping arrangement which either grounds or does not ground the word lines of a memory array depending on whether a word line is unselected or selected. More particularly, it relates to an FET device connected between each word line and ground under control of the decoder associated with each word line which either applies a potential to the gate of the FET to ground the word line when that word line is unselected or applies no potential to the gate of the FET when that particular word line is selected. The feature of this arrangement is that it permits a variation in bit line potential during any portion of the memory cycle because all unselected word lines are held at ground potential during at least the major part of the memory cycle. In addition, no d.c. power is consumed and at least one of the embodiments contains a minimum of devices.
2. Description of the Prior Art
In known circuit arrangements, a device which connects the word line driver to the word line is usually enabled or disabled depending upon the condition of an associated decoder circuit which permits the precharged gate of that device to remain charged or be discharged via the decoder circuit. When the word line is selected, the gate remains charged and the word line potential can be moved from a low potential to a higher potential. This variation in word line potential is connected to a cross-coupled bistable circuit which turns one of the cross-coupled devices ON providing ground potential at its associated node. This ground potential is connected to the gate of the other cross-coupled device turning that device OFF, thereby isolating the word line from ground during the period when the word line driver is ON. When the gate of the device which couples the word line driver to the word line is discharged (in the unselected word line mode) by providing a ground through the associated decoder circuit, no variation in word line potential can be applied to the word line and, as a consequence, the same device of the bistable circuit which was turned ON when the word line potential was varied is now turned OFF providing a high potential at its associated node. This high potential is connected to the gate of the other of the cross-coupled devices turning it ON. The latter device which is now conducting couples ground to the word line and maintains it in this state as long as it remains unselected. This arrangement for controlling the condition of the word line requires at least three FET devices and, while variation in the bit line potential is permitted during portions of the memory cell cycle, d.c. power is consumed and array density is affected because word line pitch cannot be held to a minimum. In another prior art arrangement which reduces the number of devices required for grounding the word lines to one FET per word line, and which consumes no d.c. power, all the word lines are grounded during a bit line pre-charge interval so that the potential on the bit line can be changed without adversely affecting the contents of the memory. However, once this has been done and the selected word line has been chosen via the usual decoder arrangements, all the FETs which ground the word lines are turned off and the selected word line is driven via the word line driver. Since none of the word lines are grounded at this point, it should be clear that it is not possible to change the potential (either more positively or more negatively) on the bit lines without capacitively coupling a signal to associated word lines which, in turn, can provide what would appear to be a readout of memory cells associated with those word lines. Since such readouts are usually spurious and destructive, information would assuredly be lost.
Thus, the known arrangements for grounding the word lines either do not provide for grounding during desired portions of the memory cycle or, if they do, cumbersome arrangements are utilized which take up large amounts of chip area and which consume considerable amounts of d.c. power. As higher and higher density arrangements are being reached, availability of chip area becomes a real consideration and circuits which take up a large amount of area become candidates for revision or elimination. The circuits being utilized usually represent a compromise in either versatility, chip surface area or power consumption. Since these compromises were just that, some aspect of memory operation had to suffer and no way in which versatility, power consumption and chip surface area could be melded in a cooperative way to provide the best possible compromise has been provided by the prior art. The present circuits while still a compromise, appear to represent the best possible compromise in that versatility in bit line variation is preserved while consuming no d.c. power for a minimum sacrifice in chip surface area.